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RM0008
23.3
23.3.1
SPI functional description
General description
The block diagram of the SPI is shown in Figure 207 .
Figure 207. SPI block diagram
Address and data bus
Read
Rx buffer
Serial peripheral interface (SPI)
MOSI
SPI_CR2
Shift register
TXE
IE
RXNE ERR
IE IE
0
0
TXDM RXDM
SSOE AEN AEN
MISO
LSB first
SPI_SR
Tx buffer
BSY
OVR
MOD CRC
F ERR
0
0
TXE RXNE
Write
Communication
control
0
1
SCK
Baud rate generator
BR[2:0]
LSB
FIRST
SPE BR2
BR1 BR0
MSTR CPOL CPHA
SPI_CR1
Master control logic
BIDI BIDI
MODE OE
CRC CRC
EN Next
RX
DFF ONLY SSM
SSI
NSS
ai14744
Usually, the SPI is connected to external devices through 4 pins:
●
●
●
●
MISO: Master In / Slave Out data. This pin can be used to transmit data in slave mode
and receive data in master mode.
MOSI: Master Out / Slave In data. This pin can be used to transmit data in master
mode and receive data in slave mode.
SCK: Serial Clock output for SPI masters and input for SPI slaves.
NSS: Slave select. This is an optional pin to select master/ slave mode. This pin acts as
a ‘chip select’ to let the SPI master communicate with slaves individually and to avoid
contention on the data lines. Slave NSS inputs can be driven by standard I/O ports on
the master Device. The NSS pin may also be used as an output if enabled (SSOE bit)
and driven low if the SPI is in master configuration. In this manner, all NSS pins from
devices connected to the Master NSS pin see a low level and become slaves when
they are configured in NSS hardware mode.
A basic example of interconnections between a single master and a single slave is
illustrated in Figure 208 .
Doc ID 13902 Rev 9
589/995
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